The present invention relates generally to integrated circuits, and more specifically to reducing electrical noise for an integrated circuit chip.
Integrated circuits are used widely for a variety of applications. An integrated circuit is commonly manufactured as a small die or chip of silicon material with many circuits etched onto the chip. The inputs and outputs to the circuits are typically routed to the edges of the chip and are connected to bonding pads which are linearly arranged around the perimeter of the chip. The bonding pads include signal pads which route signals to and from the circuits on the chip as well as ground and power pads for providing reference voltages to the circuits of the chip. The bonding pads are typically connected to the lead tips of a lead frame using bonding wires or a tape automated bonding (TAB) process.
In a typical integrated circuit, a bypass capacitor is connected to the bonding pads to suppress electrical noise which is caused by a large number of circuits switching simultaneously. The electrical noise can cause rise time degradation and false gate switching. Typically, the bypass capacitor is placed near the package body which surrounds the integrated circuit chip and is connected between the lead frame and the chip using bonding wires. However, a problem of using a bypass capacitor is that the bonding wires which connect the capacitor to the integrated circuit chip have an inherent inductance which can add to the electrical noise of the circuit. The longer the bonding wires, the more inductance is added, and the more electrical noise is caused. If the bonding wires are long enough, the added electrical noise cannot be suppressed by the bypass capacitor.
The problem of long bonding wires for bypass capacitors in integrated circuits has been addressed in the prior art. U.S. Pat. No. 5,049,979 of Hashemi et al. describes a combined flat capacitor and tab integrated circuit chip which provides short bonding wires to connect the capacitor to the bonding pads of the chip. This prior art combined capacitor and chip is shown in FIGS. 1a, 2b and 2 where an integrated circuit chip 10 includes a number of bonding pads 12 positioned near the edge of the chip. Ground and power bonding pads 13 are connected to ground or power circuits which provide a reference voltage for the chip 10. A flat capacitor 14 is attached to the top surface of the chip 10 and includes top electrode 16 and bottom electrode 18 with dielectric layer 19 positioned between the electrodes. A number of terminals 20 and 22 are positioned on the outer peripheries of electrode 16 and electrode 18, where inner terminals 20 are connected to electrode 16 and outer terminals 22 are connected to electrode 18. Capacitor 14 has a smaller area than the chip 16, allowing the terminals 20 and 22 to be aligned with the bonding pads 12 and provide a short interconnection distance between the capacitor terminals and bonding pads. Bonding wires 24 are used to connect the ground and power bonding pads 13 to the terminals 20 and 22 of capacitor 14, where the ground and power bonding pads are shown having a larger area.
As shown in FIG. 2, bonding wires 24 connect the ground and power bonding pads 13 of the prior art integrated circuit chip to the terminals of the capacitor 14. These wires are short so that electrical noise from inductance in the wires is not a great problem, permitting capacitor 14 to more effectively suppress the electrical noise in the circuits of chip 10. Bonding finger wires 26 are used to connect bonding pads 12 with bonding fingers 28, which are positioned in the same plane as the surface of chip 10 and spaced apart from the chip. The bonding fingers are coupled to a lead frame that provides electrical leads to the exterior of the chip package.
A problem occurs when more than one bonding wire 24 and 26 is connected to a ground or power bonding pad 13. Bonding pad 13 is typically made larger to accommodate the extra bonding wire to the capacitor. The larger bonding pad uses up more active area on the chip 10 that could be used for circuitry or other needed components. In addition, a chip must be modified to include the larger bonding pads and, possibly, include a modified bonding pad pitch for spacing the pads. This causes an integrated circuit chip to cost more and require more time to produce. Another problem with the capacitor and integrated circuit combination of the prior art is that the capacitor size is limited to a size smaller than the integrated circuit chip size. Thus, if a larger capacitor is needed to suppress a certain amount of electrical noise, the required capacitor size may not fit in the allowed space on top of the chip, leading to more electrical noise problems.
What is needed is a integrated circuit chip and capacitor that provides short bonding wires for the suppression of electrical noise and also allows a standard chip bonding pad configuration to be used with uniformly-sized bonding pads. What is also needed is an integrated circuit chip and capacitor which allow the capacitor size to be increased past the size of the integrated circuit chip for more effective noise suppression.